U.S. Pat. No. 3,737,861 shows a data processing system having an I/O bus which is connected between a traffic controller and a device control area unit containing a unique device for the attachment of each external device connected with its own unique attachment bus.
U.S. Pat. No. 4,023,142 shows a data processing system having a reliability and serviceability bus connected to the various units of a data processing system. The bus is designed to accommodate only the testing of the units and does not provide the interface necessary for data processing purposes.
U.S. Pat. No. 4,085,448 shows a data communications bus structure particularly adapted for communication between modules in a data processing system. The described bus structure contemplates the connection to an Input/Output controller with the central processing unit and does not lend itself to the direct connection of Input/Output devices beyond the confines of the central processing unit.
U.S. Pat. No. 4,246,637 shows an input/output controller which incorporates a microprocessor to specify various initial parameters concerning a data transfer, which then proceeds under the control of dedicated hardware, freeing the microprocessor for other tasks. The interface between the input/output controller and the central processing unit is a channel.
U.S. Pat. No. 4,620,278 shows an arbitration unit for a conventional data communications bus. There is no suggestion that a connected unit allow an arbitration to begin at a point in time prior to the data signal as in this invention.
U.S. Pat. No. 4,682,304 shows an I/O interface controller which contains a microprocessor controlled buffer. As is evident from the system diagram of this patent, there is no attempt to provide a uniform bus interface to the various units. The system does not contain an arbitration system for allocation of bus time, instead, the various lines are serviced on a cyclical interrupt basis.
U.S. Pat. No. 4,706,190 shows a data communications bus system in which a remote unit conditionally responds with a signal indicating delay will occur and the controlling unit terminates the transaction. The signal indicating delay does not occur in every instance and does not occur prior to the transmission of data as in the instant invention.
While the disconnection does eventually occur, there is no overlap of the arbitration sequence with the transmission of data on the bus.
U.S. Pat. No. 4,719,569 shows an arbitrator for implementation of a specific arbitration algorithm. It is clear from the description that the arbitration unit does not begin the arbitration until after the data transfer is complete, in contrast to the instant invention in which arbitration begins prior to the completion of data transfer, thereby allowing both arbitration and data transfer to proceed simultaneously.
An article "Input/Output Control Unit Busy Disconnect Mechanism", by M. J. Mitchell, Jr., IBM Technical Disclosure Bulletin, Vol. 19, No. 8, Jan. 1977, pp. 2999-3002, shows a data processing system input/output mechanism which eliminates the software overhead associated with handling the "Control Unit Busy" signal from an I/O controller. There is no showing of a system in which the remote unit provides a signal to allow arbitration to begin prior to the data transfer.
An article "Full Use of Transfer Cycles in Computers", by A. Blum, IBM Technical Disclosure Bulletin, Vol. 24, No. 10, Mar. 1982, pp. 5188-5190, shows an arbitration system in which the arbitration of the next grant begins with the data transfer of the preceding operation, requiring an additional signal which indicates the length of the current transfer. Further, this system requires the unit requesting service to continuously present a signal on a dedicated line to the controller.
An article "Bus Architecture for Passive Fault-Tolerant Command/Response System", IBM Technical Disclosure Bulletin, Vol. 29, No. 3, Aug. 1986, pp. 1313-1317 shows a dual ring bus arrangement which incorporates a fault tolerant design which reconfigures the system in the event of the failure of one unit. The system of this article does not resemble that of the subject invention.
An article "Interface Protocol for Attachment of Bus Units Having Limited I/O Pins to Processors Utilizing Several Buses", IBM Technical Disclosure Bulletin, Vol. 29, No. 10, Mar. 1987, pp. 4664-4671, shows an arrangement for interconnecting bus units within a data processing system. Unlike the system of this invention, the described system does not carry the full bus interface to all connected units.
An article "SPD Bus Throughput Accelerator", IBM Technical Disclosure Bulletin, Vol. 30, No. 4, Sept. 1987, pp. 1828-1829, shows a microprocessor test tool that can be attached to the IBM SPD bus. The system is not designed for the transfer of data, as received data is not retained, but is intended only to "stress" the bus for the purpose of testing.